The present invention relates to a semiconductor device, in particular, to a semiconductor device having a small surface mounted package.
A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used for power control switch or charge/discharge protection circuit of portable information devices is sealed in a small surface mounted package such as SOP8. Such a kind of a power MOSFET is described, for example, in Japanese Patent Laid-Open No. 2000-164869 or Japanese Patent Laid-Open No. 2000-299464.
Japanese Patent Laid-Open No. 2000-164869 discloses a technology for reducing the risk of punch-through breakdown, in a trench gate power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in a structure including a p type epitaxial layer configuring the upper layer of an n+ type silicon substrate, by forming an n type drain region so that it extends between an n+ type silicon substrate and the bottom of a trench and forming a junction between the n type drain region and the p type epitaxial layer so that it extends between the n+ type silicon substrate and the partition of the trench.
Japanese Patent Laid-Open No. 2000-299464 discloses a technology for reducing the on-resistance of a drain region by laying an epitaxial layer of a first conductivity type and a well layer of a second conductivity type over a semiconductor substrate of the first conductivity type, forming a deep trench gate, isolated by an insulating layer, in an upper side layer comprised of these epitaxial layer and well layer, forming a drain region below the trench gate, forming a source region adjacent to the trench gate and forming, over the well layer, a body region more heavily doped with an impurity than the well layer.